Approaches to Building a Quantum Computer Based on Semiconductors

Throughout this Ph.D., the quest to build a quantum computer has accelerated, driven by ever-improving fidelities of conventional qubits and the development of new technologies that promise topologically protected qubits with the potential for lifetimes that exceed those of comparable conventional qubits. As such, there has been an explosion of interest in the design of an architecture for a quantum computer. This design would have to include high-quality qubits at the bottom of the stack, be extensible, and allow the layout of many qubits with scalable methods for readout and control of the entire device. Furthermore, the whole experimental infrastructure must handle the requirements for parallel operation of many qubits in the system. Hence the crux of this thesis: to design an architecture for a semiconductor-based quantum computer that encompasses all the elements that would be required to build a large scale quantum machine, and investigate the individual these elements at each layer of this stack, from qubit to readout to control

Radio-frequency methods for Majorana-based quantum devices: fast charge sensing and phase diagram mapping

Radio-frequency (RF) reflectometry is implemented in hybrid semiconductor-superconductor nanowire systems designed to probe Majorana zero modes. Two approaches are presented. In the first, hybrid nanowire-based devices are part of a resonant circuit, allowing conductance to be measured as a function of several gate voltages ~40 times faster than using conventional low-frequency lock-in methods. In the second, nanowire devices are capacitively coupled to a nearby RF single-electron transistor made from a separate nanowire, allowing RF detection of charge, including charge-only measurement of the crossover from 2e inter-island charge transitions at zero magnetic field to 1e transitions at axial magnetic fields above 0.6 T, where a topological state is expected. Single-electron sensing yields signal-to-noise exceeding 3 and visibility 99.8% for a measurement time of 1 {\mu}s

InAs-Al Hybrid Devices Passing the Topological Gap Protocol

We present measurements and simulations of semiconductor-superconductor heterostructure devices that are consistent with the observation of topological superconductivity and Majorana zero modes. The devices are fabricated from high-mobility two-dimensional electron gases in which quasi-one-dimensional wires are defined by electrostatic gates. These devices enable measurements of local and non-local transport properties and have been optimized via extensive simulations for robustness against non-uniformity and disorder. Our main result is that several devices, fabricated according to the design's engineering specifications, have passed the topological gap protocol defined in Pikulin {\it et al.}\ [arXiv:2103.12217]. This protocol is a stringent test composed of a sequence of three-terminal local and non-local transport measurements performed while varying the magnetic field, semiconductor electron density, and junction transparencies. Passing the protocol indicates a high probability of detection of a topological phase hosting Majorana zero modes. Our experimental results are consistent with a quantum phase transition into a topological superconducting phase that extends over several hundred millitesla in magnetic field and several millivolts in gate voltage, corresponding to approximately one hundred micro-electron-volts in Zeeman energy and chemical potential in the semiconducting wire. These regions feature a closing and re-opening of the bulk gap, with simultaneous zero-bias conductance peaks at {\it both} ends of the devices that withstand changes in the junction transparencies. The measured maximum topological gaps in our devices are 20-$30\,\mu$eV. This demonstration is a prerequisite for experiments involving fusion and braiding of Majorana zero modes.Comment: Fixed typos. Fig. 3 is now readable by Adobe Reade